Gate-tunable heterojunction tunnel triodes based on 2D metal selenide and 3D silicon

Nature Electronics (2022). DOI: 10.1038/s41928-022-00849-0″ width=”800″ height=”530″/>

Credit: Miao et al, Natural electronics (2022). DOI: 10.1038/s41928-022-00849-0

Electronic engineers around the world are trying to improve the performance of devices, while reducing their energy consumption. Tunneling field-effect transistors (TFETs), an experimental class of transistors with a unique switching mechanism, could be a particularly promising solution for the development of low-power electronics.

Despite their potential, most silicon-based and III-V heterojunction TFETs exhibit low on-current densities and on-off current ratios in some modes of operation. Fabricating these transistors using 2D materials could help improve electrostatic control, potentially increasing their current densities and on/off ratios.

Researchers from the University of Pennsylvania, the Chinese Academy of Sciences, the National Institute of Standards and Technology, and the Air Force Research Laboratory have recently developed new heterojunction tunnel triodes based on van der Waals heterostructures formed from 2D metal selenide and 3D silicon. These triodes, presented in an article published in Natural electronicscould outperform other TFETs presented in the past in terms of current densities and on/off ratios.

“This paper is based on realizing tunneling transistors or switching devices based on 2D materials,” Deep Jariwala, one of the researchers who conducted the study, told TechXplore. “It’s a well-known idea that many people have been trying to work on and solve for a decade now. The problem has always been device performance to make a strong case.”

To improve the performance of tunneling switching devices in terms of ON/OFF current ratios, sub-threshold oscillation and ON current density, some studies have attempted to develop devices using only silicon and semiconductors. III-V conductors or 2D semiconductors. Although some of these proposed devices performed better than others, their performance seemed to be impaired in at least one relevant dimension.

“Thanks to our work, we have shown that when 2D InSe or WSe2 is combined with silicon, the three main performance characteristics of the device mentioned above can be simultaneously enhanced,” explained Jariwala.

To fabricate their heterojunction tunnel triodes, Jariwala and his colleagues stamped an InSe crystal onto a heavily p-doped silicon wafer. Subsequently, they created contacts using lithography, a printing method, deposited top gate dielectric and patterned gate electrodes.

“One of the main advantages of our tunable gate tunnel triodes is that they are based on silicon, which is the underlying material of all microprocessors,” Jariwala said. “In addition, they exhibit some of the steepest sub-threshold oscillations, ON/OFF current ratios, and On current density for tunneling devices, making them some of the most efficient and power-saving switches energy based on tunneling phenomena.”

In the first tests, the triodes created by the researchers achieved sub-threshold slopes as low as 6.4 mV decade-1 and average sub-threshold slopes of 34.0 mV decade-1 more than four decades of drain current. Remarkably, they also exhibited an on/off current ratio of around 106 and an on-state current density of 0.3 µA µm-1 at a drain bias of –1 V.

“We have shown that InSe works as an excellent 2D semiconductor in combination with good old silicon to enable some of the most energy-efficient switching devices,” Jariwala said. “The possible implications of this discovery are immense, since (not Moore’s Law for device reduction) is the key requirement/need of the hour for device innovation in microelectronics.”

The heterojunction tunnel triodes introduced by Jariwala and his colleagues could pave the way for the realization of more efficient low-power electronic devices. In principle, their design could also be extended to wafers, since InSe-based 2D materials can be directly grown on .

“In our next studies, we plan to increase the growth of the material to make it more practical and to reduce the dimensions of the device to improve performance even more,” added Jariwala. “Demonstrating material growth over a large area on a wafer will be a milestone that we hope to achieve by next year.”

More information:
Jinshui Miao et al, Two-dimensional metal selenide and three-dimensional silicon-based heterojunction tunneling triodes, Natural electronics (2022). DOI: 10.1038/s41928-022-00849-0

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